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Chinese to English - Standard rate: 0.10 USD per character / 40 USD per hour
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English to Chinese: ELECTRIC FUSE CIRCUIT AND ELECTRONIC COMPONENT
Source text - English This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-223428, filed on August 18, 2006, the entire contents of which are incorporated herein by reference.
The present invention relates to an electric fuse circuit and an electronic component.
Fig. 28 is a view illustrating a semiconductor memory chip having laser fuses. In a recent semiconductor memory, which has a redundant memory cell utilizing a laser fuse, it is common practice to replace a defective memory cell with the redundant memory cell. A laser fuse is a nonvolatile ROM in which information is written by irradiating a laser beam onto a wiring conductive layer to disconnect the fuse (e.g., when being connected, it is electrically conductive, i.e., “0”; when being disconnected, it is electrically nonconductive, i.e., “1”) and the address of the defective memory cell is stored in the ROM so that the redundant memory cell will take over. There is a known phenomenon such as degradation of the refresh characteristics of a DRAM in a memory chip 1601 due to heat or the like produced when it is packaged. However, a laser beam LS cannot be radiated after packaging. Accordingly, a method has been studied in which an electrically writable electric fuse is used as a nonvolatile ROM on which the address of a defective memory cell is stored to accomplish the replacement with a redundant memory cell.
Fig. 29 is a diagram illustrating an exemplary configuration of an electric fuse circuit. Hereinafter, a field-effect transistor is referred to simply as a transistor. An electric-fuse capacitor 101 is connected between a voltage VRR and a node n3. The gate, the drain, and the source of an n-channel transistor 102, which is a protection transistor, are connected to a voltage VPP, the node n3, and a node n2, respectively. The voltage VPP is, for example, 3 V. The gate, the drain, and the source of an n-channel transistor 103, which is a write circuit, are connected to a write signal WRT, the node n2, and the ground, respectively.
Next, the configuration of a read circuit 110 will be explained. The gate, the drain, and the source of an n-channel transistor 111 are connected to a read signal RD, the node n2, and a node n4, respectively. The gate, the drain, and the source of an n-channel transistor 113 are connected to a node n5, the node n4, and the ground via a resistor 114, respectively. The gate, the source, and the drain of a p-channel transistor 112 are connected to the node n5, a voltage VII, and the node n4, respectively. The voltage VII is, for example, 1.6 V. The input terminal and the output terminal of a negative AND (NAND) circuit 115, which is connected to the power-supply voltage VII, are connected to the node n4 and the wire of a signal RSTb, and the node n5, respectively. The input terminal and the output terminal of a negation (NOT) circuit 116 are connected to the node 5 and the wire of a signal EFA, respectively.
In addition, a current cutoff circuit in Japanese Patent Application Laid-Open No. 2002-197889 includes a first field-effect transistor and a second field-effect transistor whose current paths are connected in series to a first fuse and a second fuse, respectively, a pad electrode connected to the gate of the first field-effect transistor, a load resistor connected between a power source and the gate of the first field-effect transistor, and a fuse circuit for determining the conductivity of the second field-effect transistor, in accordance with whether or not a defect should be repaired.
Additionally, in Japanese Patent Application Laid-Open No. 2001-338495, a semiconductor memory device, included in a DRAM-redundant-row decoder, is described in which a plurality of n-channel MOS transistors whose gates each receives a predecoded signal allocated to a corresponding word line are connected in series between respective ones of terminals of corresponding fuses and the ground potential GND.
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